1. Field of the Invention
The present invention relates to a making of landing pad, and more particularly a method for increasing the area of landing pad.
2. Description of the Prior Art
Owing to the gradual concentration of integrated circuits, there is a trend of reducing the size of semiconductor device and the distance between devices with each passing day. Therefore, more advanced processing technology and better device structures are highly demanded, urgently.
Taking the production of dynamic random access memory (DRAM) as an example, it is also progressing toward the trend of shrinkage. That is, the gate width used for the word line has become smaller and smaller and there is also a trend in the reduction of every device size and the distance between devices. Under this particular situation, an alignment accuracy shift from the mask would often result in a very serious harm toward the processing field. The so-called alignment accuracy shift is simply an error between the etching point defined by the mask pattern and the actual contact point reserved on the substrate. This results in a shift of the hole formed after etching away from the predicted location. This shift is very likely to end up with unrecoverable consequences.
Take the formation of a capacitor as a further example. Fundamental transistors are formed on top of a substrate, moreover, a landing pad is located between the neighboring gates and a dielectric layer is positioned on top. The process follows in making a contact between capacitor and landing pad for defining the location of a contact window. Furthermore, a contact hole is etched all the way to the landing pad. At the same time when semiconductor devices are becoming smaller, the distance between two gates would be shorter as well and this will cause the area of the landing pad between two gates to become smaller. Herein, the alignment accuracy shift produced after the contact hole is etched would likely make the contact hole to be etched all the way to the gate. According to FIG. 1, when this contact hole is filled with conductor and also forms a capacitor, it is very likely to cause conductivity between the gate and the capacitor. Short circuit phenomena between word line and bit line occurs straight away.
In the situation where current masking and photolithography technology still cannot overcome the problem mentioned above totally, changes must be made toward the process in order to reduce short circuit probability. Therefore, a new method for forming landing pad needs to be developed. The method should not only overcome the problem carried by alignment accuracy shift. It also needs to adapt the principle of semiconductor device shrinkage in order to follow the trend of future development.